 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| osd lsis m pd6461 m pd6462 m pd6464a m pd6465 m pd6466 document no. s13197ej1v0umj1 (1st edition) publication date october 2000 n cp(k) 1998 user? manual printed in japan
2 [memo] 3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. ms-dos, windows, and windows nt are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. 4 m8e 00. 4 the information in this document is current as of may, 1998. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). 5 preface target users this users manual is intended for users who understand the functions of the m pc6461, m pd6462, m pd6464a, m pd6465, and m pd6466 on-screen character display cmos lsis (osd lsis) and who will design and develop application systems for them. purpose the purpose of this users manual is to help users understand the basic functions of osd lsis. hardware configurations that appear in this manual are illustrative examples only, and there is no plan for their mass production. configuration this users manual consists of the following chapters. ? chapter 1 overview ? chapter 2 basic operation ? chapter 3 application examples ? chapter 4 faq ? chapter 5 development tools how to read this manual readers of this manual should have a general understanding of electrical and logic circuits, microcontrollers, and video signal processing. legend data significance : higher digits on the left and lower digits on the right active low representation : (overscore over pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation : binary ............... or 0b decimal ............ hexadecimal .... 0x 6 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. data sheets m pd6461 (document number: s12588e) m pd6462 (document number: s12593e) m pd6464a, m pd6465 (document number: s11043e) m pd6466 (document number: s10991e) users manuals osd lsis (this manual) osd lsi character pattern editor for windows? (to be prepared) character pattern editor for on-screen display lsi note (document number: s10153e) note this manual is for ms-dos? (for pc-9801) and pc dos? (for ibm pc/at?). information rom code ordering method (document number: c10302j) note note this document number is that of japanese version. caution the related documents listed above may be changed without notice. be sure to use the latest documents for design and other purposes. 7 contents chapter 1 overview ................................................................................................................... 13 1.1 list of osd lsis ................................................................................................................ 14 1.2 ordering information ........................................................................................................ 15 1.3 pin configurations ............................................................................................................ 16 1.4 block diagrams ................................................................................................................. 24 chapter 2 basic operation ..................................................................................................... 27 2.1 osd lsi configuration ..................................................................................................... 27 2.1.1 dot clock oscillation circuit ..................................................................................................... 27 2.1.2 timing generator ..................................................................................................................... 29 2.1.3 horizontal control section ....................................................................................................... 29 2.1.4 vertical control section ............................................................................................................ 30 2.1.5 video ram control section ..................................................................................................... 30 2.1.6 video ram .............................................................................................................................. 3 1 2.1.7 character generator rom ...................................................................................................... 31 2.1.8 output controller ..................................................................................................................... 31 2.2 basic operation of a video-system osd lsi ............................................................... 32 2.2.1 quadruple/4fsc crystal oscillation circuit ................................................................................ 32 2.2.2 synchronization separation circuit ......................................................................................... 34 2.2.3 video signal output section .................................................................................................... 39 2.3 basic operation of an rgb-system osd lsi ............................................................... 41 2.3.1 synchronization protection circuit .......................................................................................... 41 2.3.2 r, g, b, and blk outputs when rgb + v c1 + v c2 is selected ............................................. 45 2.3.3 r, g, b, and blk outputs when rgb + blanking corresponding to rgb (3blk) is selected ..................................................................................................... 47 2.4 characters .......................................................................................................................... 49 2.4.1 character display .................................................................................................................... 49 2.4.2 character patterns .................................................................................................................. 50 2.5 commands ......................................................................................................................... 50 2.5.1 command format .................................................................................................................... 50 2.5.2 command list .......................................................................................................................... 51 2.6 osd lsi power-on initialization .................................................................................... 56 chapter 3 application examples ......................................................................................... 57 3.1 video-system osd lsi application examples ............................................................. 57 3.1.1 sample m pd6464a or m pd6465 application circuits ............................................................. 57 3.1.2 composite synchronization signal (csync) separation circuit .............................................. 60 3.1.3 sample application for separate video signal input .............................................................. 63 3.1.4 sample application for ntsc direct mode ............................................................................ 64 8 3.2 rgb-system osd lsi application examples ............................................................... 66 3.2.1 sample m pd6461a or m pd6462 application circuit ............................................................... 66 3.2.2 sample m pd6466 application circuit ...................................................................................... 67 3.3 external clock forced input to lc oscillation circuit section ................................. 68 chapter 4 faq ............................................................................................................................... 69 4.1 all osd lsis ...................................................................................................................... 69 4.2 video-system osd lsis ( m pd6464a and m pd6465) ..................................................... 73 4.3 rgb-system osd lsis ( m pd6461, m pd6462, and m pd6466) ...................................... 76 chapter 5 development tools ............................................................................................. 79 5.1 overview of development tools ..................................................................................... 79 5.2 concerning osd lsi mask rom ordering .................................................................... 83 9 list of figures (1/2) figure no. title page 1-1 sample uses of osd lsis (rgb-system osd lsi: camcorder) .................................................. 13 1-2 m pd6464a or m pd6465 pin configuration (top view) ...................................................................... 16 1-3 m pd6461 or m pd6462 pin configuration (top view) ........................................................................ 18 1-4 m pd6466 pin configuration (top view) ............................................................................................. 21 1-5 m pd6464a and m pd6465 block diagram .......................................................................................... 24 1-6 m pd6461 and m pd6462 block diagram ............................................................................................ 25 1-7 m pd6466 block diagram .................................................................................................................... 26 2-1 osd lsi basic block diagram ........................................................................................................... 27 2-2 dot clock oscillation equivalent circuit ............................................................................................ 28 2-3 horizontal control section .................................................................................................................. 29 2-4 vertical control section ...................................................................................................................... 30 2-5 video ram control section ................................................................................................................ 30 2-6 quadruple/4fsc crystal oscillation circuit ......................................................................................... 33 2-7 synchronization separation circuit section ...................................................................................... 35 2-8 sample horizontal synchronization signal correction circuit timing charts .................................. 36 2-9 video signal output section equivalent circuit ................................................................................ 39 2-10 v syt and v ped levels of composite video signal ............................................................................. 40 2-11 display character vertical jitter generation mechanism ................................................................. 42 2-12 synchronization protection circuit operation (mode 1) .................................................................... 43 2-13 synchronization protection circuit operation (mode 2) .................................................................... 43 2-14 synchronization protection circuit operation (mode 3) .................................................................... 44 2-15 synchronization protection circuit operation (mode 4) .................................................................... 44 2-16 display character vertical jitter prevention mechanism .................................................................. 45 2-17 output pins: sample r, g, b, and blk output images when rgb + v c1 + v c2 is selected ....... 46 2-18 sample r, g, b, and blk output images when rgb + 3blk is selected .................................... 47 2-19 sample use of blanking signals corresponding to rgb ................................................................. 48 2-20 character display ............................................................................................................................... 49 3-1 sample m pd6464a or m pd6465 application circuit (when quadruple oscillation is selected) ......................................................................................... 58 3-2 sample m pd6464a or m pd6465 application circuit (when 4fsc crystal oscillation is selected) ...................................................................................... 59 3-3 composite synchronization signal separation circuit ...................................................................... 60 3-4 sample application circuit for separate video signal input ............................................................. 63 3-5 sample application circuit for ntsc direct mode ............................................................................ 65 3-6 sample m pd6461 or m pd6462 application circuit ............................................................................ 66 3-7 sample m pd6466 application circuit ................................................................................................. 67 3-8 timing chart for external clock forced input ................................................................................... 68 10 list of figures (2/2) figure no. title page 4-1 character display area image 1 C when ntsc and pal signals are input (for equivalent display start position and dot clock frequency) .................................................... 72 4-2 character display area image 2 C when ntsc and pal signals are input (for center display) ............................................................................................................................. 72 4-3 sample display using character inversion ....................................................................................... 77 5-1 rom verification board connection diagram for rgb display ....................................................... 80 5-2 rom verification board connection diagram for vcr display ....................................................... 81 5-3 video-system osd lsi evaluation board connection diagram ...................................................... 82 5-4 rgb-system osd lsi evaluation board connection diagram ....................................................... 82 5-5 osd lsi mask rom code ordering procedure (for fd order reception) .................................... 83 11 list of tables table no. title page 1-1 list of osd lsis ............................................................................................................................... .. 14 1-2 ordering information ........................................................................................................................... 15 1-3 list of m pd6464a and m pd6465 pin functions ................................................................................ 17 1-4 list of m pd6461 and m pd6462 pin functions ................................................................................... 20 1-5 list of m pd6466 pin functions ........................................................................................................... 23 2-1 m pd6464a or m pd6465 internal video signal level ......................................................................... 40 2-2 command data transfer format ....................................................................................................... 50 2-3 m pd6464a or m pd6465 command tables ........................................................................................ 51 2-4 m pd6461 or m pd6462 command tables (msb first) ....................................................................... 52 2-5 m pd6461 or m pd6462 command tables (lsb first) ........................................................................ 53 2-6 m pd6466 command tables (msb first) ............................................................................................ 54 2-7 m pd6466 command tables (lsb first) ............................................................................................. 55 3-1 ntsc direct mode setting command ............................................................................................... 64 12 [memo] 13 chapter 1 overview the on-screen character display cmos lsi (osd lsi) is used to display character data on various types of monitor screens. the size of one character is 12 (horizontal) by 18 (vertical) dots, and up to 12 lines of 24 columns (288 characters) can be displayed. the character types are determined by the rom capacity of each product. nec has 128-character ( m pd6462, m pd6464a), 256-character ( m pd6461, m pd6465), and 512-character ( m pd6466) osd lsis. also, the nec osd lsis are broadly divided into video-system osd lsis ( m pd6464a, m pd6465) and rgb-system osd lsis ( m pd6461, m pd6462, m pd6466) according to their use. by combining it with a microcontroller, a video- system osd lsi controls not only the program screen of a deck-type vcr or ld player, but also various indicators (such as the tape counter). an rgb-system osd lsi controls the display of the counter, time, date, and other indicators on the viewfinder of a camcorder, the transcription of the time, date, and other indicators on a video tape, and the display of the channel or other indicators on a tv screen. this users manual describes the operation of osd lsis and presents several practical examples of their use. figure 1-1. sample uses of osd lsis (rgb-system osd lsi: camcorder) lens camera section, synchronization separation section, color signal processing section, etc. character mix rgb decoder image signal hsync, vsync v r , v g , v b , v blk v c1 , blk1 v c2 , blk2 osd microcontroller character mix character mix rec tape batt rec tape batt pm 1:30 1997.12 lcd (color) viewfinder (black and white) recording system (deck) recorded contents 14 chapter 1 overview 1.1 list of osd lsis table 1-1. list of osd lsis video-system rgb-system sample uses tv, video, video cd camcorder, dvd, lcd tv, digital still camera product name m pd6464a m pd6465 m pd6461 m pd6462 m pd6466 character type 128 256 256 128 512 number of display characters 12 lines 24 columns (288 characters) dot matrix 12 (horizontal) 18 (vertical) dots character color single color (white) (select brightness 8 colors level for the screen from 75ire/95ire) character size (unit: lines) 1 and 2 1 , 2 , 3 , and 4 (simultaneous horizontal and vertical specification) (independent horizontal and vertical specifications) character color inversion none black characters (no framing) black characters (unit: characters) (framing control disabled) white characters (framing control enabled) character left-right inversion none available (cannot (unit: characters) be used when blinking is specified) blinking (unit: characters) blinking ratio is 1:1 (blinking frequency can be selected for the entire screen from the three options corresponding to approximately 0.5, 1, and 2 hz) internal video signal color white, black, blue, or green none white or blue (effective only for rgb-system output) background (unit: screen) no background, black framing, black-on-white, black filling background color single color (black) 8 colors (rgb-system output) or (unit: screen) single color (black: v c1 and v c2 system output) framing color (unit: screen) single color (black) 2 colors (white and black) supported video signal ntsc, psl, pal-m, secam, method or pal-n ( m pd6464a only) video signal input/output composite video signal no input/output system character signal output character signal and blanking signal rgb + 3blk or rgb + v c1 + v c2 (for m pd6461 and m pd6462, select according to mask code option; for m pd6466, select according to command) video ram data clear video ram data can be cleared by the video ram batch clear command and the power-on clear function interface with microcontroller serial input type of 8-bit variable word length operation power supply range 4.5 to 5.5 v 2.7 to 5.5 v packages 24-pin sdip 20-pin ssop 20-pin ssop 20-pin ssop 24-pin sop 24-pin sop 24-pin sop 15 chapter 1 overview 1.2 ordering information table 1-2. ordering information part number package nec standard rom code number video- m pd6464acs- 24-pin plastic shrink dip (300 mils) 001 system m pd6464agt- 24-pin plastic sop (375 mils) 101 m pd6465cs- 24-pin plastic shrink dip (300 mils) 001 m pd6465gt- 24-pin plastic sop (375 mils) 101 rgb- m pd6461gs- 20-pin plastic shrink sop (300 mils) 101: msb first, 3-line unit setting, rbg + 3blk, system option b, lc oscillation 102: msb first, 3-line unit setting, rbg + v c1 + v c2 , option b, lc oscillation m pd6461gt- 24-pin plastic sop (375 mils) m pd6462gs- 20-pin plastic shrink sop (300 mils) 001: msb first, 3-line unit setting, rbg + v c1 + v c2 , option c, lc oscillation m pd6466gs- 20-pin plastic shrink sop (300 mils) 001 m pd6466gt- 24-pin plastic sop (375 mils) 201 remarks 1. indicates rom code suffix. 2. for the m pd6461 and m pd6462, the following are selected according to the mask code option (for the m pd6466, they can be selected according to the initialization command or the cmdct pin). for details, refer to the data sheet for each product. ? data transfer : lsb first or msb first ? vertical display start position : 3-line unit setting or 9-line unit setting ? pin selection : rbg + v c1 + v c2 or rgb + 3blk ? output selection : option a, option b, or option c ? dot clock : lc oscillation or external clock input 16 chapter 1 overview 1.3 pin configurations figure 1-2. m pd6464a or m pd6465 pin configuration (top view) 24-pin plastic shrink dip (300 mils) m pd6464acs- m pd6465cs- 24-pin plastic sop (375 mils) m pd6464agt- m pd6465gt- remark indicates rom code suffix. clk : clock input cs : chip select input csyin : composite synchronization signal input data : serial data input fsci : f sc signal input fsco : frequency error output gnd : ground hsyo : horizontal synchronization signal output n.c. : no connection nre : noise reduction constant append osc in : lc oscillation input osc out : lc oscillation output pcl : power-on clear secam : secam subcarrier input test : test pin v blk : blanking signal output vbsi : composite video signal input vbso : composite video signal output v c : character signal output v cnt : video signal output level adjustment v dd : power supply vsyo : vertical synchronization signal output xosi : quadruple oscillation input xoso : quadruple oscillation output 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n.c. csyin vsyo hsyo v blk v c 17 chapter 1 overview table 1-3. list of m pd6464a and m pd6465 pin functions pin no. pin symbol pin name function 1 clk clock input inputs clock for data read. data input to the data pin is read at the rising edge of the clock input to this pin. 2 cs chip select input serial transfer can be acknowledged by making this cs pin low. 3 data serial data input inputs control data. data is read in synchronization with the clock input to the clk pin. 4v dd power supply supplies power to the ic. 5 osc out lc oscillation output these are input and output pins of an oscillator that generates dot clocks. 6 osc in lc oscillation input connect a coil and a capacitor to these pins for oscillation. 7 pcl power-on clear power-on clear pin. make this pin high on power application. it initializes the internal circuitry of the ic. 8 gnd ground ground pin of the ic. 9 fsci fsc signal input inputs color subcarrier signal (fsc) when quadruple oscillation is selected. connect it to gnd or v cc when 4fsc crystal oscillation is selected. 10 fsco frequency error output frequency error output signal of the 4 multiplier. leave it open when 4fsc crystal oscillation is selected. 11 xoso quadruple oscillation output the quadruple oscillator lc for internal video signal generation is connected 12 xosi quadruple oscillation input to these pins. a crystal oscillator also can be connected. 13 v c character signal output character signal output pin, which is high active. 14 v blk blanking signal output this pin outputs a blanking signal that cuts the video signal. it corresponds to v c output and is high active. 15 hsyo horizontal synchronization outputs a horizontal synchronization signal separated from the composite signal output synchronization signal. 16 vsyo vertical synchronization outputs a vertical synchronization signal separated from the composite signal output synchronization signal. 17 csyin composite synchronization inputs a composite synchronization signal for synchronization separation. signal input always input this signal when external video signal mode is used. the input polarity is positive synchronization. 18 n.c. no connection free pin. leave this pin open. 19 test test pin test mode select pin. generally, connect this pin to gnd. 20 nre noise reduction constant constant append pin for noise reduction. append 21 vbso composite video signal output outputs a composite video signal with which the character signal is mixed. 22 secam secam subcarrier input secam subcarrier signal mixing pin. when a mode other than secam is selected, leave this pin open. 23 v cnt video signal output level adjusts the output level adjustment of the composite video signal and adjustment luminance signal. 24 vbsi composite video signal input inputs a composite video signal. inputs a signal with the leading edge clamped, consisting of a negative synchronization and positive video signal. 18 chapter 1 overview figure 1-3. m pd6461 or m pd6462 pin configuration (top view) 20-pin plastic shrink sop (300 mils) m pd6461gs- m pd6462gs- 24-pin plastic sop (375 mils) m pd6461gt- remarks 1. indicates rom code suffix. 2. the symbols enclosed in parentheses are set by the mask code option (rgb + blanking corresponding to rgb). clk 1 cs 2 data 3 pcl 4 v dd 5 ck out 6 osc out 7 osc in 8 test 9 gnd 10 20 19 18 17 16 15 14 13 12 11 hsync vsync v b v g v r v blk (b blk ) v c2 (g blk ) blk2 (r blk ) v c1 blk1 clk 1 cs 2 n.c. 3 data 4 pcl 5 v dd 6 7 osc out 8 osc in 9 test 10 24 23 hsync vsync n.c. v c1 gnd n.c. 11 12 22 21 20 19 18 17 16 15 14 13 blk1 n.c. v b v g v r v blk (b blk ) v c2 (g blk ) blk2 (r blk ) ck out 19 chapter 1 overview b blk : blanking b blk1, blk2 : blanking output 1, 2 ck out : clock output clk : clock input cs : chip select data : data input g blk : blanking g gnd : ground hsync : horizontal synchronous signal input n.c. : no connection osc in : oscillator input osc out : oscillator output pcl : power-on clear r blk : blanking r test : test v b : character signal output v blk : blanking signal output for v r , v g , and v b v c1 , v c2 : character signal output 1, 2 v dd : power supply v g : character signal output v r : character signal output vsync : vertical synchronous signal input 20 chapter 1 overview table 1-4. list of m pd6461 and m pd6462 pin functions note 2 pin no. note 1 pin symbol pin name note 2 function 1 clk clock input inputs clock for data read. data input to the data pin is read at the rising edge of the clock input to this pin. 2 cs chip select input serial transfer can be acknowledged by making this cs pin low. 3 (4) data serial data input inputs control data. data is read in synchronization with the clock input to the clk pin. 4 (5) pcl power-on clear power-on clear pin. make this pin high on power application. it initializes the internal circuitry of the ic. 5 (6) v dd power supply supplies power to the ic. 6 (7) ck out clock output checks the oscillation frequency. it uses n-channel open-drain output. 7 (8) osc out lc oscillation input/output these are input and output pins of an oscillator that generates dot 8 (9) osc in (osc in : external clock input) clocks. connect a coil and a capacitor to these pins for oscillation. (when external clock input is selected by the mask option, the external clock (clock synchronized with hsync) is input. osc out is left open.) 9 (10) test test pin ic test pin. connect this pin to gnd. 10 (11) gnd ground connect this pin to the system gnd. 11 (14) blk1 blanking signal output 1 this pin outputs a blanking signal that cuts the video signal. it corresponds to v c1 output and is high active. (when blanking corresponding to rgb is selected by the mask option, the logical sum of r blk , g blk , and b blk is output.) 12 (15) v c1 character signal output 1 outputs the character signal. it is high active. (when blanking corresponding to rgb is selected by the mask option, the logical sum of v r , v g , and v b is output.) 13 (16) blk2 blanking signal output 2 this pin outputs a blanking signal that cuts the video signal. it (r blk ) (blanking r) corresponds to v c2 output and is high active. (the blanking signal corresponding to v r output is output. it is high active.) 14 (17) v c2 character signal output 2 outputs the character signal. it is high active. (g blk ) (blanking g) (the blanking signal corresponding to v g output is output. it is high active.) 15 (18) v blk blanking signal output this pin outputs a blanking signal that cuts the video signal. it (b blk ) (blanking b) corresponds to v r , v g , and v b output and is high active. (the blanking signal corresponding to v b output is output. it is high active.) 16 (19) v r character signal output character signal output pin, which is high active. 17 (20) v g 18 (21) v b 19 (23) vsync vertical synchronization inputs the vertical synchronization signal. input using negative signal input synchronization. 20 (24) hsync horizontal synchronization inputs the horizontal synchronization signal. input using negative signal input synchronization. (3,12,13,22) n.c. no connection free pin. notes 1. the numbers enclosed in parentheses are pin numbers for the m pd6461gt- . 2. the symbols and names enclosed in parentheses are set by the mask code option (rgb + blanking corresponding to rgb). 21 chapter 1 overview figure 1-4. m pd6466 pin configuration (top view) 20-pin plastic shrink sop (300 mils) m pd6466gs- 24-pin plastic sop (375 mils) m pd6466gt- remarks 1. indicates rom code suffix. 2. the symbols enclosed in parentheses are set by the initialization command (rgb + blanking corresponding to rgb). clk 1 cs 2 data 3 pcl 4 v dd 5 cmdct 6 osc out 7 osc in 8 test 9 gnd 10 20 19 18 17 16 15 14 13 12 11 hsync vsync v b v g v r v blk (b blk ) v c2 (g blk ) blk2 (r blk ) v c1 blk1 clk 1 cs 2 n.c. 3 data 4 pcl 5 v dd 6 cmdct 7 osc out 8 osc in 9 test 10 24 23 hsync vsync n.c. v c1 gnd n.c. 11 12 22 21 20 19 18 17 16 15 14 13 blk1 n.c. v b v g v r v blk (b blk ) v c2 (g blk ) blk2 (r blk ) 22 chapter 1 overview b blk : blanking b blk1, blk2 : blanking output 1, 2 clk : clock cmdct : command control cs : chip select data : data input g blk : blanking g gnd : ground hsync : horizontal synchronous signal input n.c. : no connection osc in : oscillator input osc out : oscillator output pcl : power-on clear r blk : blanking r test : test v b : character signal output v blk : blanking signal output for v r , v g , and v b v c1 , v c2 : character signal output 1, 2 v dd : power supply v g : character signal output v r : character signal output vsync : vertical synchronous signal input 23 chapter 1 overview table 1-5. list of m pd6466 pin functions note 2 pin no. note 1 pin symbol pin name note 2 function 1 clk clock input inputs clock for data read. data input to the data pin is read at the rising edge of the clock input to this pin. 2 cs chip select input serial transfer can be acknowledged by making this cs pin low. 3 (4) data serial data input inputs control data. data is read in synchronization with the clock input to the clk pin. 4 (5) pcl power-on clear power-on clear pin. make this pin high on power application. it initializes the internal circuitry of the ic. 5 (6) v dd power supply supplies power to the ic. 6 (7) cmdct command control switches between lsb-first and msb-first input for commands. when this pin is low, lsb-first input is used. when it is high, msb- first input is used. when using lsb-first input, this pin can be left open. 7 (8) osc out lc oscillation input/output these are input and output pins of an oscillator that generates dot 8 (9) osc in (osc in : external clock input) clocks. connect a coil and a capacitor to these pins for oscillation. (when external clock input is selected by the initialization command, the external clock (clock synchronized with hsync) is input. osc out is left open.) 9 (10) test test ic test pin. connect this pin to gnd. 10 (11) gnd ground connect this pin to the system gnd. 11 (14) blk1 blanking signal output 1 this pin outputs a blanking signal that cuts the video signal. it corresponds to v c1 output and is high active. (when blanking corresponding to rgb is selected by the command, the logical sum of r blk , g blk , and b blk is output.) 12 (15) v c1 character signal output 1 outputs the character signal. it is high active. (when blanking corresponding to rgb is selected by the command, the logical sum of v r , v g , and v b is output.) 13 (16) blk2 blanking signal output 2 this pin outputs a blanking signal that cuts the video signal. it (r blk ) (blanking r) corresponds to v c2 output and is high active. (the blanking signal corresponding to v r output is output. it is high active.) 14 (17) v c2 character signal output 2 outputs the character signal. it is high active. (g blk ) (blanking g) (the blanking signal corresponding to v g output is output. it is high active.) 15 (18) v blk blanking signal output this pin outputs a blanking signal that cuts the video signal. it (b blk ) (blanking b) corresponds to v r , v g , and v b output and is high active. (the blanking signal corresponding to v b output is output. it is high active.) 16 (19) v r character signal output character signal output pin, which is high active. 17 (20) v g 18 (21) v b 19 (23) vsync vertical synchronization inputs the vertical synchronization signal. input using negative signal input synchronization. 20 (24) hsync horizontal synchronization inputs the horizontal synchronization signal. input using negative signal input synchronization. (3,12,13,22) n.c. no connection free pin. notes 1. the numbers enclosed in parentheses are pin numbers for the m pd6466gt- . 2. the names enclosed in parentheses are set by the initialization command (rgb + blanking corresponding to rgb). 24 chapter 1 overview 1.4 block diagrams figure 1-5. m pd6464a and m pd6465 block diagram 3 data 1 clk data input shift register data buffer register instruction decoder control signal external/ internal register ntsc/ pal/ pal-m/ secam/ pal-n note register character size register horizontal address register horizontal position counter write address counter horizontal address counter horizontal size counter vertical position counter vertical address counter vertical size counter vertical address register 4v dd 8 gnd 19 test 7 pcl 2 cs oscilla- tion circuit timing generator 6 osc in 5 osc out cosc in cosc out synchroni- zation signal separation circuit mode selection synchroni- zation signal generator quadruple/4fsc crystal oscillation circuit display control data register 17 csyin 15 hsyo 16 vsyo 10 fsco 9 fsci 11 xoso 12 xosi character data 7 bits ( pd6464a) or 8 bits ( pd6465) 288 words blink data 1 bit 288 words back- ground control data register video ram character generator rom 12 18 bits 128 words ( pd6464a) or 256 words ( pd6465) output controller v c 24 13 14 20 21 22 23 v blk nre vbso secam v cnt vbsi losc note pd6464a only data selector m m m m m 25 chapter 1 overview figure 1-6. m pd6461 and m pd6462 block diagram instruction decoder data input shift register control signal character size register display position horizontal address register write address counter horizontal size counter horizontal position counter horizontal address counter display position vertical address register video ram chara- cter data 8 bits 288 words color data 3 bits 288 words blink data 1 bit 288 words invert data 1 bit 288 words output specifi- cation data 1 bit 288 words data clk cs ck out osc in osc out hsync vsync oscilla- tion circuit synchro- nization protection circuit vertical size counter vertical position counter vertical address counter character generator rom 12 18 bits 256 words ( pd6461) or 128 words ( pd6462) output controller v r v g v b v blk v c1 blk1 v c2 blk2 (b blk )(g blk )(r blk ) back- ground control data register display control data register test v dd gnd pcl data selector remark the symbols enclosed in parentheses are set by the mask code option (rgb + blanking corresponding to rgb). m m 26 chapter 1 overview figure 1-7. m pd6466 block diagram cmdct data input shift register data clk cs instruction decoder ? control signal display control register character size register horizontal address register write address counter horizontal size counter horizontal position counter horizontal address counter vertical address register oscil- lation circuit synchro- nization protection circuit test v dd gnd pcl chara- cter data 9 bits 288 words color data 3 bits 288 words blink data 1 bit 288 words invert data 1 bit 288 words output specifi- cation data 1 bit 288 words video ram back- ground control data register hsync vsync vertical position counter vertical size counter vertical address counter output controller v r v blk v b v g blk2 v c2 blk1 v c1 (g blk )(r blk ) (b blk ) character generator rom 12 18 bits 512 words osc in osc out remark the symbols enclosed in parentheses are set by the initialization command (rgb + blanking corresponding to rgb). data selector 27 chapter 2 basic operation this chapter describes the basic operation of an osd lsi. 2.1 osd lsi configuration an osd lsi consists of a dot clock oscillation circuit, timing generator, horizontal control section, vertical control section, video ram control section, video ram, character generator rom, display/background control register section, and output controller. the osd lsi, which is controlled by command data sent from a microcontroller, displays the character data stored in the character generator rom ( m pd6462 and m pd6464a: 128 characters; m pd6461 and m pd6465: 256 characters; m pd6466: 512 characters) on the display screen. figure 2-1. osd lsi basic block diagram 2.1.1 dot clock oscillation circuit the dot clock oscillation circuit consists of the osd lsi and an externally connected lc circuit. with an rgb- system osd lsi, external clock input can be selected (for the m pd6461 and m pd6462, this is selected by the mask code option; for the m pd6466, it is selected by the initialization command). horizontal control section display/background control register section vertical control section dot clock oscillation circuit timing generator output controller hsync video-system rgb-system : input from synchronization separation circuit : input from synchronization separation protection circuit vsync ? ? ? ? ? command data video ram character generator rom 12 18 bits number of characters video ram control section output of various types of signals dot clock oscillation on/off 28 chapter 2 basic operation figure 2-2. dot clock oscillation equivalent circuit (a) when lc oscillation is selected (b) when external clock input is selected ( m pd6461, m pd6462, or m pd6466) remark when lc oscillation is on, the dot clock oscillation circuit is controlled as follows by the timing generator while hsync is low. when display is on : dot clock oscillation stopped when display is off : dot clock oscillation the dot clock frequency (fosc) when lc oscillation is on can be calculated using the following formulas. fosc = 1 [hz] (2 p? lc) c = c in ? c out [f] (c in + c out ) by setting l = 33 m h, c in = 5 to 30 pf (trimmer capacitor), and c out = 30 pf, the circuit can be used in the lc oscillation frequency range (fosc = 6 to 8 mhz) recommended by nec for operation. the actual circuit will have a lower frequency than the calculated value due to effects such as the stray capacitance of the pins or delay within the lsi. high level when oscillation is off (from timing generator) to timing generator osc out osc in always high level (from timing generator) to timing generator osc out osc in open external clock input 29 chapter 2 basic operation 2.1.2 timing generator the timing generator generates various types of timing signals according to horizontal/vertical synchronization signals input from the dot clock oscillation circuit, synchronization separation circuit, synchronization signal generator (video-system osd lsi) or synchronization protection circuit (rgb-system osd lsi) commands from the microcontroller (such as lc oscillation on/off, crystal oscillation on/off, or display on/off, etc.). 2.1.3 horizontal control section the horizontal display start position of a character is determined by counting dot clocks from the rising edge of the horizontal synchronization signal (hsync). the character is displayed at the position corresponding to this horizontal display start position and the specified video ram column address. each block reset is synchronized with hsync. if hsync is not supplied within the osd lsi, the character is not displayed correctly, since no reset occurs. figure 2-3. horizontal control section character size register horizontal address register horizontal address counter to video ram control section hsync dot clock horizontal size counter horizontal position counter to vertical control section from timing generator ? ? ? ? ? command data 30 chapter 2 basic operation 2.1.4 vertical control section the vertical display start position of a character is determined by counting rising edges of the horizontal synchronization signal (hsync) from the rising edge of the vertical synchronization signal (vsync). the character is displayed at the position corresponding to this vertical display start position and the specified video ram line address. the character type to be displayed is set by the character generator rom line address control. figure 2-4. vertical control section 2.1.5 video ram control section the video ram control section controls video ram addresses. when a video ram batch clear command is executed, the display off code is written to all addresses (288 words) of video ram. figure 2-5. video ram control section from character size register vertical address register vertical address counter to video ram control section vsync vertical size counter vertical position counter from timing generator ? ? ? hsync command data video ram batch clear command video ram batch clear control circuit data selector video ram write-address counter write-address control command display-address data from horizontal and vertical control sections video ram data 31 chapter 2 basic operation 2.1.6 video ram the video ram maintains data set in character units corresponding to a 12 line by 24 column display area. 2.1.7 character generator rom the character generator rom stores a character font. the number of characters is determined by the rom capacity. the character generator rom for a video-system osd lsi can have a capacity of 128 characters ( m pd6464a) or 256 characters ( m pd6465). for an rgb-system osd lsi, can have a capacity of 128 characters ( m pd6462), 256 characters ( m pd6461), or 512 characters ( m pd6466). 2.1.8 output controller the output controller controls the display of characters, backgrounds, and other output. 32 chapter 2 basic operation 2.2 basic operation of a video-system osd lsi this section describes the basic operation of the circuits of a video-system osd lsi ( m pd6464a or m pd6465). 2.2.1 quadruple/4f sc crystal oscillation circuit figure 2-6 shows a block diagram of a quadruple/4f sc crystal oscillation circuit. with the m pd6464a or m pd6465, quadruple oscillation or 4f sc crystal oscillation is selected according to the externally connected circuit and oscillation mode control command. since the 4f sc signal generated by the oscillation circuit is used as the reference clock for synchronization signal generation when internal video signal mode is set and the f sc signal is used as the reference clock for internal video signal generation and for synchronization separation in the synchronization separation circuit, a crystal oscillation control command must be used to set crystal oscillation to on when generating characters. the operation of this circuit when each mode is selected is explained below. (1) when quadruple oscillation is selected the f sc signal must be input from the fsci pin (pin 9) (see figure 3-1 sample m pd6464a or m pd6465 application circuit (when quadruple oscillation is selected) ). the 4f sc signal is generated by an externally connected lc oscillator and internal circuits of the m pd6464a or m pd6465. also, the phase of the signal obtained by dividing the 4f sc signal generated by lc oscillation into 4 parts is compared with the phase of the f sc signal input to the fsci pin, and the phase differential is converted to a voltage value and output from the fsco pin (pin 10). a 4f sc signal that is synchronized with the external f sc signal is generated by varying the varactor diode capacitance according to this voltage. selecting this mode reduces the crystal oscillator and enables the installation area and cost to be reduced. (2) when 4f sc crystal oscillation is selected connect a crystal resonator (frequency: 4f sc ) between the xoso pin (pin 11) and xosi pin (pin 12) and connect a capacitor (approx. 30 pf) between the xoso pin (pin 11) and ground (gnd) and connect a trimmer capacitor (5 to 30 pf) between the xosi pin (pin 12) and ground (gnd) (see figure 3-2 sample m pd6464a or m pd6465 application circuit (when 4f sc crystal oscillation is selected) ). this crystal oscillator generates the 4f sc signal, and the f sc signal is generated by dividing this 4f sc signal into four parts. 33 chapter 2 basic operation figure 2-6. quadruple/4fsc crystal oscillation circuit (a) when quadruple oscillation is selected (b) when 4fsc crystal oscillation is selected xosi 12 xoso 11 fsco 10 fsci 9 phase detector to synchronization signal generator 4f sc crystal oscillation on/off to synchronization separation circuit or internal video signal generation circuit f sc 4.7 h 47 pf 18 pf 20 k w 20 k w 1.5 k w 1 f 1000 pf 1/4 ntsc, pal-m pal, secam : h : l vd 100 k w 5.1 k w 0.01 f + 2200 pf f sc m m m xosi 12 xoso 11 fsco 10 fsci 9 4f sc f sc 4f sc 5 to 30 pf 30 pf open v cc or gnd 1/4 to synchronization signal generator crystal oscillation on/off to synchronization separation circuit or internal video signal generation circuit phase detector 34 chapter 2 basic operation 2.2.2 synchronization separation circuit when external video signal mode is selected, the synchronization separation circuit uses the fsc signal generated by the quadruple/4fsc crystal oscillation circuit to separate the horizontal synchronization signal (hsync) and vertical synchronization signal (vsync) from the composite synchronization signal (csync). the vertical synchronization signal sampling circuit uses the fsc signal to sample vsync from csync by counting down when csync is high and counting up when it is low. also, the horizontal synchronization signal sampling circuit can prevent synchronization signals from being omitted or noise from being generated due to invalid signals because it contains an on-chip horizontal synchronization signal correction (hsync autogeneration) circuit. when internal video signal mode is selected, vsync and hsync are generated by the synchronization signal generator by using the 4fsc signal generated by the quadruple/4fsc crystal oscillation circuit section. the operation of the horizontal synchronization signal correction (hsync autogeneration) circuit is outlined below (see figure 2-8 for sample timing charts). (1) hsync width the m pd6464a recognizes a signal of at least 0.2 m sec as hsync, and the m pd6465 recognizes a signal of at least 0.8 m sec. signals having smaller widths are ignored. (2) hsync cycle no external signal can be sampled for an interval of 61.2 m sec after hsync is sampled. (3) hsync autogeneration the hsync cycle is monitored, and if no external hsync is input in a 61.2 to 64.5 m sec interval after hsync is sampled, a pseudo hsync is autogenerated and output. the sampling of signals is not inhibited after the autogeneration of the pseudo hsync. the external signal that is input next is treated as hsync to accelerate the move back to the regular hsync (if the sampling of signals were inhibited after the autogeneration of the pseudo hsync, the auto-generation interval would continue, resulting in a loss of synchronization between the external hsync and the hsync used for display inside the osd lsi). according to the operation described above, the pseudo hsync is output even if no external csync is input. however, no pseudo vsync is autogenerated. 35 chapter 2 basic operation figure 2-7. synchronization separation circuit section composite synchroni- zation signal positive synchroni- zation input vertical synchroni- zation signal negative synchroni- zation input horizontal synchroni- zation signal negative synchroni- zation input 17 csyin 16 vsyo 15 hsyo vsync vsync hsync hsync mode selection synchroni- zation signal generator to timing generator video signal mode selection internal/external mode selection 4f sc f sc from quadruple/crystal oscillation circuit ? vertical synchroniza- tion signal sampling circuit up/down counting circuit synchroni- zation signal separation circuit section horizontal synchronization signal sampling circuit counter, horizontal synchronization correction (autogeneration) circuit 36 chapter 2 basic operation figure 2-8. sample horizontal synchronization signal correction circuit timing charts (1/3) (a) when regular signals are input odd fields even fields remark the numbers enclosed in parentheses are vertical display counter values within the m pd6464a or m pd6465. 3h 4h 5h 6h 7h 8h 9h 10h 11h 12h csync input mask (0) (0) (0) (1) (2) (3) (4) (5) hsync output vsync output 61.2 s m 266h (3) 268h (5) 270h (7) 272h (9) 274h (11) csync input mask (0) (0) (0) (1) (2) (3) (4) (5) hsync output vsync output 61.2 s m 37 chapter 2 basic operation figure 2-8. sample horizontal synchronization signal correction circuit timing charts (2/3) (b) hsync autogeneration example odd fields even fields notes 1. indicates that one pulse within the csync signal is missing. 2. this is an autogenerated hsync signal within the m pd6464a or m pd6465. remark the numbers enclosed in parentheses are vertical display counter values within the m pd6464a or m pd6465. 3h 4h 5h 6h 7h note 1 note 2 note 2 8h 9h 10h 11h 12h csync input mask (0) (0) (0) (1) (2) (3) (4) (5) (6) hsync output vsync output 61.2 s 64.5 s m m note 1 note 2 note 2 64.5 s 266h (3) 268h (5) 270h (7) 272h (9) 274h (11) csync input mask (0) (0) (0) (1) (2) (3) (4) (5) (6) hsync output vsync output 61.2 s m m 38 chapter 2 basic operation figure 2-8. sample horizontal synchronization signal correction circuit timing charts (3/3) (c) change in hsync output due to input mask after autogeneration when no masking is performed after autogeneration when masking is performed after autogeneration csync input mask hsync output auto- genera- tion return csync input mask hsync output auto- genera- tion auto- genera- tion auto- genera- tion . . . . . . . . . . . . . . . . . . . . . . 39 chapter 2 basic operation 2.2.3 video signal output section the video signal output section mixes character information with a video signal input from an external source or with an internally generated video signal and outputs the mixed signal. with the m pd6464a or m pd6465, set the v cnt pin voltage to 2.5 v to use the internal/external video signal amplitude level at 1 v p-p , and set the v cnt pin voltage to 5 v to use it at 2 v p-p . in addition, the corresponding sync-chip level and pedestal level of the composite video signal input from an external source must match the internal video signal level (see table 2-1 ). if the video signal amplitude level, sync-chip level, and pedestal level are not matched with the internal/external video signal, the character levels will differ in external video signal mode and internal video signal mode. for details about the adjustment method, refer to the data sheet. figure 2-9. video signal output section equivalent circuit note set the v cnt pin voltage to 5 v when the internal video signal amplitude level is 2 v p-p , and set the voltage to 2.5 v when the amplitude level is 1 v p-p . remark the switch operations are as follows. sw0: controlled by the output control section according to the character/background level, color burst/ color phase (for internal video signal mode), etc. sw1: this is on when the secam method is set for the external video signal mode. sw2: this is on during the video signal output interval when internal video signal mode is selected. v dd v dd v dd 100 pf nre 5 k w v cnt note sw0 vbsi vbso secam sw1 sw2 40 chapter 2 basic operation table 2-1. m pd6464a or m pd6465 internal video signal level v cnt pin voltage output level internal video signal sync-chip level: pedestal level: control command amplitude level v syt v ped 2.5 v specifies 1 v p-p 1 v p-p 1 v 1.29 v 5.0 v specifies 2 v p-p 2 v p-p 1 v 1.58 v remark v dd = 5.0 v figure 2-10. v syt and v ped levels of composite video signal vbso gnd v syt v ped 41 chapter 2 basic operation 2.3 basic operation of an rgb-system osd lsi this section describes the basic operation of the circuits of an rgb-system osd lsi ( m pd6461, m pd6462, or m pd6466). 2.3.1 synchronization protection circuit an osd lsi determines the vertical display start position of a character by counting rising edges of the horizontal synchronization signal (hsync) from the rising edge of the vertical synchronization signal (vsync). as shown in figure 2-11 (a), when the vsync and hsync rising edges overlap and vsync has jitter, the display start position is indefinite depending on whether or not the hsync rising edge that overlaps vsync is counted as the first hsync after the vsync rising edge. if a count error occurs, since the display start position shifts 1h, vertical jitter of the display character occurs (the character on the screen shifts in 1h units; see figure 2-11 (c) ). the synchronization protection circuit eliminates hsync counting errors by autogenerating a pseudo hsync signal internally so that no vertical jitter of the display character is caused by a shift of the display starting position. this circuit sets certain areas (areas a, b, c, and d note in figures 2-12 to 2-15) according to the character dot clock after the hsync rising edge and generates a pseudo hsync signal to prevent vertical jitter corresponding to the hsync and vsync signals input within their range. by counting the pseudo hsync signal, display output is performed with no vertical jitter (the circuit operates so that the hsync and vsync status is always kept fixed). note the area widths in the m pd6461, m pd6462, or m pd6466 are as follows. area a width: hsync width + 12/fosc ( m pd6461 or m pd6462) with the m pd6466, the area a width is as follows according to the horizontal display start position. hsync width + 7/fosc (horizontal display start position = 28 + 12n: n = 0,1,2,) hsync width + 10/fosc (horizontal display start position = 25 + 12n: n = 0,1,2,) hsync width + 13/fosc (horizontal display start position = 22 + 12n: n = 0,1,2,) hsync width + 16/fosc (horizontal display start position = 31 + 12n: n = 0,1,2,) area b width: 48/fosc area c width: 12/fosc area d width: other than areas a, b, and c fosc: dot clock frequency the synchronization protection circuit operates as described below. 42 chapter 2 basic operation figure 2-11. display character vertical jitter generation mechanism (a) relationship between hsync and vsync when vertical jitter occurs (b) character pattern (c) display character vertical jitter generation model (when the count error occurs at the first of an odd field) remark if vsync shifts in the vicinity of the hsync rising edge, display character vertical jitter occurs according to whether or not the first hsync signal of the odd fields is counted as the first signal. 1 2 3 4 5 6 7 8 9 264 265 266 267 268 269 270 271 odd field line no. even field line no. vsync hsync 123 1 2 3 4 5 6 7 8 9 264 265 266 267 268 269 270 271 odd field line no. even field line no. vsync hsync 12 occurrence of display character vertical jitter : odd field display character : even field display character 12 3 1 2 count number when a counting omission occurred hsync vsync vsync shift display character vertical jitter occurs according to whether or not this hsync signal is counted as the first hsync signal due to vsync vibration. 43 chapter 2 basic operation (1) mode 1 figure 2-12. synchronization protection circuit operation (mode 1) note this is output only when a pseudo hsync signal has been output by the previous field. if the vsync rising edge is input before the hsync rising edge (area d), the count begins with the hsync(1) rising edge. however, if a pseudo hsync signal has been output by the previous field, the pseudo hsync (1') signal is also output by the current field in area c. the count begins with this pseudo hsync (1') rising edge, and then subsequent hsync signals are counted. (2) mode 2 figure 2-13. synchronization protection circuit operation (mode 2) if a vsync signal is input in the period (area a) determined by the hsync low period and a certain number of dot clocks from hsync rising edge, a pseudo hsync (1') signal is output within the internal circuitry of the osd lsi in area c, the count begins with this rising edge, and then subsequent hsync signals are counted. vsync hsync pseudo hsync b a 1 d c d 1 note vsync hsync pseudo hsync b a 1 d c d 1 44 chapter 2 basic operation (3) mode 3 figure 2-14. synchronization protection circuit operation (mode 3) note this is output only when a pseudo hsync signal has been output by the previous field. when the vsync rising edge is input in area b, if a pseudo hsync signal has been output by the previous field, the pseudo hsync(1') signal is also output by this field in area c. the count begins with this pseudo hsync (1') rising edge, and then subsequent hsync signals are counted. however, if a pseudo hsync signal has not been output by the previous field, no pseudo hsync signal is output by this field, and the count begins with the next hsync rising edge that was input. (4) mode 4 figure 2-15. synchronization protection circuit operation (mode 4) notes 1. this is not counted. the count begins with the next hsync. 2. no pseudo hsync signal is output regardless of the status in the previous field. when the vsync rising edge is input in area c, the pseudo hsync(1') signal is not output regardless of the status in the previous field, and the count begins with the hsync rising edge that was input next. vsync hsync pseudo hsync b a 1 d c d 1 note vsync hsync pseudo hsync b a d c d 1 note 2 1 note 1 45 chapter 2 basic operation figure 2-16. display character vertical jitter prevention mechanism (a) character pattern (b) display character vertical jitter prevention model (when the vsync shift occurs at the first of an odd field) remark even if vsync shifts in the vicinity of the hsync rising edge, the pseudo hsync signal is generated by the action of the synchronization protection circuit, and no display character vertical jitter occurs. 2.3.2 r, g, b, and blk outputs when rgb + v c1 + v c2 is selected figure 2-17 shows the relationships among the r, g, b, and blk outputs when the mask option (for the m pd6461 or m pd6462) or initialization command (for the m pd6466) is used to set the output pins to rgb + v c1 + v c2 mode. 1 2 3 4 5 6 7 8 9 264 265 266 267 268 269 270 271 odd field line no. even field line no. vsync hsync pseudo hsync 123 odd field line no. even field line no. vsync hsync 2 1 3 1 2 3 4 5 6 7 8 9 264 265 266 267 268 269 270 271 prevention of display character vertical jitter : odd field display character : even field displa y character pseudo hsync 46 chapter 2 basic operation figure 2-17. output pins: sample r, g, b, and blk output images when rgb + v c1 + v c2 is selected remark the waveform of each output pin represents the output on the dashed line (horizontal) in the middle of the character. white character no framing, no background with framing, no background white character black framing v r v g v b v blk v r v g v b v blk v r v g v b v blk v r v g v b v blk no framing, with background white character red background with framing, with background with framing, with background white character black framing red background red character no framing, no background with framing, no background red character black framing v r v g v b v blk v r v g v b v blk v r v g v b v blk v r v g v b v blk no framing, with background red character red background red character white framing red background with framing, with background black character no framing, no background with framing, no background black character white framing v r v g v b v blk v r v g v b v blk v r v g v b v blk v r v g v b v blk no framing, with background blue character blue background black character white framing blue background 47 chapter 2 basic operation 2.3.3 r, g, b, and blk outputs when rgb + blanking corresponding to rgb (3blk) is selected figure 2-18 shows the relationships among the r, g, b, and blk outputs when the mask option (for the m pd6461 or m pd6462) or initialization command (for the m pd6466) is used to set the output pins to rgb + 3blk mode. figure 2-18. sample r, g, b, and blk output images when rgb + 3blk is selected remarks 1. the waveform of each output pin represents the output on the dashed line (horizontal) in the middle of the character. 2. v c1 is the logical sum of v r , v g , and v b , and blk1 is the logical sum of r blk , g blk , and b blk . no framing, with background r g red character: i green character: j background: blue v r r blk v g g blk v b b blk v c1 blk1 b with framing, with background r red character: i green character: j background: blue black framing v r r blk v g g blk v b b blk v c1 blk1 h h h b g with framing, with background r red character: i green character: j background: blue white framing v r r blk v g g blk v b b blk v c1 blk1 h h b g no framing, with background r g red character: i green character: j background: yellow v r r blk v g g blk v b b blk v c1 blk1 r+g r + g with framing, with background r red character: i green character: j background: yellow black framing v r r blk v g g blk v b b blk v c1 blk1 h h h l l g with framing, with background r red character: i green character: j background: yellow white framing v r r blk v g g blk v b b blk v c1 blk1 h h g no framing, with background black character: i white character: j background: blue v r r blk v g g blk v b b blk v c1 blk1 b with framing, with background black character: i white character: j background: blue black framing v r r blk v g g blk v b b blk v c1 blk1 h h h h h b with framing, with background black character: i white character: j background: blue white framing v r r blk v g g blk v b b blk v c1 blk1 h b r + g l l l 48 chapter 2 basic operation to provide the same image data to two screens and simultaneously display different characters for each of them (such as displaying only red characters on the viewfinder in a camcorder and transcribing only green characters onto the video tape), use blanking signals corresponding to rgb as shown in figure 2-19 (a). by using blanking signals corresponding to rgb even when white framing is set, you can display only single-color characters. however, the colors of the character portion and framing portion are identical as shown in figure 2-19 (b). figure 2-19. sample use of blanking signals corresponding to rgb (a) when no framing is set (b) when white framing is set no framing, with background (use blk1) r r g red character: i green character: j background: blue v r r blk display only red character (use r blk ) v r r blk v g g blk display only green character (use g blk ) g v g g blk v b b blk v c1 blk1 b h h with framing, with background (use blk1) display only red character (use r blk ) red character: i green character: j background: blue white framing v r r blk v g g blk v r r blk display only green character (use g blk ) v g g blk v b b blk v c1 blk1 h h b g g r r 49 chapter 2 basic operation 2.4 characters 2.4.1 character display an osd lsi displays the character generator rom contents in a 12-line by 24-column display area. figure 2-20 shows an image of the display area. figure 2-20. character display (a) character position control remark the horizontal display start position (a) and vertical display start position (b) are controlled by the character position control command. (b) sample display image when interlace is used (when a = 3h is set) display area (12 lines 24 columns) a b horizontal synchronization signal (hsync) vertical synchronization signal (vsync) odd field line no. even field line no. : odd field display character : even field displa y character 1 2 3 4 5 6 7 8 9 264 265 266 267 268 269 270 271 character pattern 50 chapter 2 basic operation 2.4.2 character patterns characters can be designed by using a character pattern editor (for details, see chapter 5 development tools ) that can be rented from nec. for inquiries related to character pattern editor rental, contact an nec distributor or nec sales representative. for information about the character patterns of nec standard products, refer to the data sheet of each product. 2.5 commands 2.5.1 command format osd lsi control commands are of variable word length in 8-bit units and are input in serial. three types of commands are available: 1-byte commands consisting of 8 bits for the instruction and data combined, 2-byte commands, and 2-byte contiguous commands that enable abbreviated input to be performed. table 2-2 shows the command data transfer format of each product. table 2-2. command data transfer format product name command data transfer format video-system m pd6464a, 6465 msb first rgb-system m pd6461, 6462 msb first or lsb first can be selected by using mask option m pd6466 msb first or lsb first can be selected by using cmdct pin 51 chapter 2 basic operation 2.5.2 command list this section introduces the command tables of each product. for details about commands, refer to the data sheet of each product. table 2-3. m pd6464a or m pd6465 command tables 1-byte commands (msb) function d7 d6 d5 d4 d3 d2 d1 d0 video ram batch clear 00000000 display control 0001d0lcbl1bl0 internal video signal color control 0010rgb0 background control 00110bs1bs00 internal/external mode control, crystal oscillation control 01000e/i0 xosc video signal method control 01001 n/p2 n/p1 n/p0 oscillation method control 010100xf c 0 2-byte commands (msb) function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 display position control 100000v4v3v2v1v0h4h3h2h1h0 write address control 1000100ar3ar2ar1ar0ac4ac3ac2ac1ac0 output level control 1001000vpd000001vc1vc0 character size control 100110000s000ar3ar2ar1ar0 test mode note 10110000t7t6t5t4t3t2t1t0 note cannot be used 2-byte contiguous command (msb) function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 display character control 110000bl0 c7 note c6 c5 c4 c3 c2 c1 c0 note fixed to 0 ( m pd6464a) 52 chapter 2 basic operation table 2-4. m pd6461 or m pd6462 command tables (msb first) 1-byte commands (msb) function d7 d6 d5 d4 d3 d2 d1 d0 video ram batch clear 00000000 character display control 0001dolcbl1bl0 background color/framing color control 0010rgbbfc 3-system independent display on/off 01110doadobdoc character inversion on/off 0011100 bcre 2-byte commands (msb) function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 character display position control 100000v4v3v2v1v0h4h3h2h1h0 write address control 1000100ar3ar2ar1ar0ac4ac3ac2ac1ac0 output pin control 10011100v c2 v c1 0 0 ar3 ar2 ar1 ar0 character size control 100110000s00ar3ar2ar1ar0 3-system background control 1011001ba1ba0bfabb1bb0bfbbc1bc0bfc test mode note 1011000t8t7t6t5t4t3t2t1t0 note cannot be used 2-byte contiguous command (msb) function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 display character control 1 1 rv r g b bl v c2 c7 note c6 c5 c4 c3 c2 c1 c0 note with the m pd6462, character bit 7 is fixed to dont care. 53 chapter 2 basic operation table 2-5. m pd6461 or m pd6462 command tables (lsb first) 1-byte commands (lsb) function d0 d1 d2 d3 d4 d5 d6 d7 video ram batch clear 00000000 character display control bl0 bl1 lc do 1000 background color/framing color control bfc b g r 0100 3-system independent display on/off doc dob doa 01110 character inversion on/off bcre 0011100 2-byte commands (lsb) function d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 character display position control v3 v4 000001h0h1h2h3h4v0v1v2 write address control ar3 0010001ac0ac1ac2ac3ac4ar0ar1ar2 output pin control 00111001ar0ar1ar2ar300v c1 v c2 character size control 00011001ar0ar1ar2ar300s0 3-system background control ba1 1001101bfcbc0bc1bfbbb0bb1bfaba0 test mode note t80001101t0t1t2t3t4t5t6t7 note cannot be used 2-byte contiguous command (lsb) function d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 display character control v c2 bl b g r rv 1 1 c0c1c2c3c4c5c6 c7 note note with the m pd6462, character bit 7 is fixed to dont care. 54 chapter 2 basic operation table 2-6. m pd6466 command tables (msb first) 1-byte commands (msb) function d7 d6 d5 d4 d3 d2 d1 d0 video ram batch clear 00000000 display control 0001dolcbl1bl0 background color/framing color control 0010rgbbfc 3-system independent display on/off 01110doadobdoc character color inversion on/off 0111100 bcre blue back on/off 01111clr0bb character address bank switching 0111111bc output switch control 0 1 0 s3a s3b sw4 sw2 sw1 2-byte commands (msb) function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 character display position control 100000v4v3v2v1v0h4h3h2h1h0 write address control 1000100ar3ar2ar1ar0ac4ac3ac2ac1ac0 output pin control 10011100od1od000ar3ar2ar1ar0 character size control 100110sv1sv0sh1sh000ar3ar2ar1ar0 3-system background control 1011001ba1ba0bfabb1bb0bfbbc1bc0bfc initial settings 101101000brrsop1op0cocvstosc test mode note 10110000t7t6t5t4t3t2t1t0 note cannot be used 2-byte contiguous command (msb) function d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 display character control 1 1 rv r g b bl v c2 c7 c6 c5 c4 c3 c2 c1 c0 55 chapter 2 basic operation table 2-7. m pd6466 command tables (lsb first) 1-byte commands (lsb) function d0 d1 d2 d3 d4 d5 d6 d7 video ram batch clear 00000000 display control bl0 bl1 lc do 1000 background color/framing color control bfc b g r 0100 3-system independent display on/off doc dob doa 01110 character color inversion on/off bcre 0011100 blue back on/off bb 0 clr 11110 character address bank switching bc 1111110 output switch control sw1 sw2 sw4 s3b s3a 0 1 0 2-byte commands (lsb) function d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 character display position control v3 v4 000001h0h1h2h3h4v0v1v2 write address control ar3 0010001ac0ac1ac2ac3ac4ar0ar1ar2 output pin control 00111001ar0ar1ar2ar300od0od1 character size control sv0 sv1 011001ar0ar1ar2ar300sh0sh1 3-system background control ba1 1001101bfcbc0bc1bfbbb0bb1bfaba0 initial settings 00101101oscvstcocop0op1rsbr0 test mode note 00001101t0t1t2t3t4t5t6t7 note cannot be used 2-byte contiguous command (lsb) function d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 display character control v c2 bl b g r rv 1 1 c0c1c2c3c4c5c6c7 56 chapter 2 basic operation 2.6 osd lsi power-on initialization because the internal status of the osd lsi is indefinite on power application, initialize the osd lsi by making the pcl pin low for a fixed interval and executing a power-on clear operation. when the power-on clear operation has been performed, the various control register settings are as follows. ? test mode is cleared. ? all character data of the video ram (12 lines by 24 columns) are set to display off data. ? blinking data are set to off. ? video ram write address is set to line 0, column 0. ? character size is set to 1 (standard size) on all lines. ? display is set to off, and lc oscillation is set to on. ? the line specification set by output pin control is cleared ( m pd6461, m pd6462, or m pd6466). ? initial defaults are set ( m pd6466). ? display on/off setting of each output system is set to off ( m pd6466). ? no background and no framing are set for all 3 systems ( m pd6466). ? blue back is set to off ( m pd6466). ? character address bank is set to the low-order (0) bank ( m pd6466). the time required for the power-on clear operation can be calculated by using the following expression. t (time required for power-on clear) = t pcll + {video ram clear time} = 10 ( m s min.) + {10 ( m s) + 12/fosc (mhz) 288 [ m s]} fosc (mhz): lc oscillation frequency or external clock frequency remarks 1. do not input a command during execution of the power-on clear operation. 2. a dot clock is required to clear video ram. when external clock input is selected, input a dot clock from the osc in pin before executing the power-on clear or video ram batch clear operation. 3. the power-on clear operation, which is a hardware reset due to a signal input to the pcl pin, performs initialization that includes video ram clear and test mode clear operations. in contrast, the video ram batch clear operation, which is a software reset that performs initialization according to a command (software), does not execute a test mode clear operation. 57 chapter 3 application examples 3.1 video-system osd lsi application examples 3.1.1 sample m pd6464a or m pd6465 application circuits 58 chapter 3 application examples figure 3-1. sample m pd6464a or m pd6465 application circuit (when quadruple oscillation is selected) cautions 1. the clamp circuit is not necessary when the sync-chip level (1 v dc) can be directly input to pin 24. 2. pin 20 is connected so as to reject unwanted radiation. 3. this application circuit is assumed to input 2-v p-p video signals. 4. a product equivalent to 1sv163 can be used as a vd (varactor diode). 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n.c. csyin vsyo hsyo v blk v c 1 clk 2 cs 3 data + + + + 59 chapter 3 application examples figure 3-2. sample m pd6464a or m pd6465 application circuit (when 4fsc crystal oscillation is selected) cautions 1. the clamp circuit is not necessary when the sync-chip level (1 v dc) can be directly input to pin 24. 2. pin 20 is connected so as to reject unwanted radiation. 3. this application circuit is assumed to input 2-v p-p video signals. 4. connect pin 9 to gnd or v cc (it cannot be left open). leave pin 10 open. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n.c. csyin vsyo hsyo v blk v c 1 clk 2 cs 3 data + + + 60 chapter 3 application examples 3.1.2 composite synchronization signal (csync) separation circuit figure 3-3. composite synchronization signal separation circuit (a) sample composite synchronization signal separation circuit r 1 = 5.1 k w , r 2 = 1.2 k w , r 3 = 1 k w , r 4 = 220 w , r 5 = 100 k w , r 6 = 10 k w , r 7 = 1 k w , r 8 = 2.2 k w , r 9 = 10 k w , c 1 = 10 m f, c 2 = 1 m f, c 3 = 1000 pf (b) composite signal separation waveform image r 1 r 3 r 5 r 2 q1 a b + + c 1 c 2 composite video signal (2 v p-p ) v c c i sp i x r 4 r 8 r 9 c 3 q2 r 6 r 7 q3 v dd = 5 composite synchronization signal (positive synchronization) 0.7 v dd (min.) 0.3 v dd (max.) input to pin 17 of the pd6464a or pd6465 m m v c v c1 v c2 v c3 d v c t 1 4.7 s t 2 58.86 s mm 61 chapter 3 application examples the operation of the circuit shown in figure 3-3 and the method of determining the slice level are described below. the voltages at points a, b, and c in figure 3-3 (a) are given as follows. a = v l , b = v l + v c , c = v h remark v l : sync-chip voltage at point a v h : threshold voltage of q2 let r 5 >> r 4 and let c 2 be sufficiently large. then from the relationship v = idt, the values of d v c when the capacitor is charged and discharged are as follows. when charged: d v c = v h C (v l + v c1 ) t 1 1 r 4 c 2 when discharged: d v c = v l + v c2 t 2 1 r 5 c 2 v c is stabilized at a location where the values of d v c when the capacitor is charged and discharged are the same (let the average voltage of v c = v c3 ). from a macro viewpoint, the synchronization base is clamped at v c3 , and the comparison is performed at the q2 threshold voltage (v h ). therefore, the slice level v s is as follows. v s = v h C (v c3 + v l ) letting the values of d v c be equal here (v c1 @ v c2 @ v c1 ) gives the following equation. v h C (v l + v c1 ) t 1 = v l + v c2 t 2 r 4 r 5 substituting v s = v h C (v l + v c3 ) and eliminating common terms gives the following equation. v s 1 + t 2 = v h t 2 r 4 r 5 t 1 r 5 t 1 letting >> here gives the following equation. v s = v h r 4 t 2 r 5 t 1 in figure 3-3, since v h = 2.7 v, r 4 = 220 w , r 5 = 100 k w , since t 1 = 4.7 m s and t 2 = 58.86 m s, the slice level v s is as follows. v s = 2.7 220 58.86 100000 4.7 @ 74 mv 1 c 1 r 4 t 2 r 5 t 1 62 chapter 3 application examples making v s small is advantageous for horizontal synchronization separation, but disadvantageous for vertical synchronization separation. conversely, making v s large causes synchronization aberrations (jitter) due to noise in horizontal synchronization separation. therefore, the constants must be optimized depending on the signal that is input. although a sufficiently large value is selected for the c 2 capacitance value compared with the charge/discharge current, if it is set too large, the transient response characteristic worsens, and it will not be able to follow a sudden apl fluctuation of the input signal. in the circuit shown in figure 3-3 (a), the input is set to a capacitor combination to simplify measurement. as a result, it is weak relative to apl fluctuation. therefore, when the circuit is actually configured, using a sync-chip clamp circuit to establish the electric potential of the leading edge of synchronization before inputting it to q1 in figure 3- 3 (a) makes it strong relative to apl fluctuation. caution with the circuit shown in figure 3-3, the hsync synchronization signal width after composite synchronization signal separation may be large compared with the input signal due to the circuit configuration. as a result, when calculating the command continuous input enable times according to the formulas shown in the data sheet for each product, the hsync synchronization signal width after composite synchronization signal separation in the circuit shown in figure 3-3 must be used for the hsync synchronization signal width (t hwl1 or t hwl2 ). 63 chapter 3 application examples 3.1.3 sample application for separate video signal input figure 3-4. sample application circuit for separate video signal input (a) sample application circuit (b) pin waveform models 24 vbsi clamp circuit composite synchronization signal separation circuit chrominance and v blk signal mixing circuit y: brightness signal 21 vbso 17 csyin y + v c + v blk 14 v blk c + v blk c: chrominance signal 13 v c pd6464a, 6465 m y c c + v blk v c v blk y + v c + v blk 64 chapter 3 application examples 3.1.4 sample application for ntsc direct mode for ntsc mode, using the command shown in table 3-1 sets and clears ntsc direct mode. when ntsc direct mode is used, the ic can be used only with fsc input. when ntsc direct mode is not used (or is cleared), the ic is in normal mode (quadruple/crystal oscillation). figure 3-5 shows a sample application circuit when this command is used. the usage method shown here is a reference example only and is not recommended by nec. table 3-1. ntsc direct mode setting command caution note the following when setting ntsc direct mode. 1. set the fsc input amplitude to 500 mv p-p (min.). 2. set the crystal oscillation command to oscillation off. 3. set the video signal method control command to ntsc. 4. the internal video signal colors are the three colors; white, black, and blue (green cannot be displayed). d15 1 d14 0 d13 1 d12 1 d11 0 d10 0 d9 0 d8 0 d7 1 d6 1 d5 1 d4 1 d3 di1 d2 di0 d1 0 d0 0 di1 0 1 0 1 di0 0 1 1 0 function ntsc direct mode control bits clear ntsc direct mode set ntsc direct mode setting prohibited (invalid operation will occur) 65 chapter 3 application examples figure 3-5. sample application circuit for ntsc direct mode cautions 1. the clamp circuit is not necessary when the sync-chip level (1 v dc) can be directly input to pin 24. 2. pin 20 is connected so as to reject unwanted radiation. 3. this application circuit is assumed to input 2-v p-p video signals. 4. to set ntsc direct mode, the ntsc direct mode control command must be input. 5. for the internal video signal color, select from the three colors; white, black, and blue (green cannot be displayed). 6. input an fsc signal having an amplitude of at least 500 mv p-p to pin 9. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk cs data v dd osc out osc in pcl gnd fsci fsco xoso xosi vbsi v cnt secam vbso nre test n.c. csyin vsyo hsyo v blk v c 1 clk 2 cs 3 data + + + 66 chapter 3 application examples 3.2 rgb-system osd lsi application examples 3.2.1 sample m pd6461a or m pd6462 application circuit figure 3-6. sample m pd6461 or m pd6462 application circuit notes 1. set the cr constant so that the power-on clear standards are satisfied. 2. this circuit enables the number of external components to be reduced and the oscillation frequency to be easily adjusted by using an lc module manufactured by toukou co., ltd. (part no.: q285ncis- 11181). 3. set the following when using external clock input. osc in pin: external clock input, osc out pin: open 4. the symbols enclosed in parentheses are set by the mask code option (rgb + blanking corresponding to rgb). remarks 1. the numbers enclosed in parentheses are the pin numbers for the m pd6461gt- . 2. with the m pd6461gt- , the effect of noise through the lead frame can be reduced by connecting the n.c. pins (pin numbers 3, 12, 13, and 22) to gnd. clk cs data pcl v dd ck out osc out osc in test gnd 10 f 33 h connect to microcontroller input hsync and vsync using negative synchronization output 30 pf 5 to 30 pf lc module pin number <1> lc module pin number <3> 0.01 f 10 f v dd 100 k w note 1 note 2 + + 1 (1) 2 (2) 3 (4) 4 (5) 5 (6) 6 (7) 7 (8) note 3 8 (9) note 3 9 (10) 10 (11) 20 (24) 19 (23) 18 (21) 17 (20) 16 (19) 15 (18) 14 (17) 13 (16) 12 (15) 11 (14) hsync vsync v b v g v r v c1 blk1 v blk v c2 blk2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pd6461gs/gt, 6462gs (b blk ) note 4 (g blk ) note 4 (r blk ) note 4 m m m m m 67 chapter 3 application examples 3.2.2 sample m pd6466 application circuit figure 3-7. sample m pd6466 application circuit notes 1. set the cr constant so that the power-on clear standards are satisfied. 2. this circuit enables the number of external components to be reduced and the oscillation frequency to be easily adjusted by using an lc module manufactured by toukou co., ltd. (part no.: q285ncis- 11181). 3. set the following when using external clock input. osc in pin: external clock input, osc out pin: open 4. the symbols enclosed in parentheses are set by the initialization command (rgb + blanking corresponding to rgb). 5. when this is open, lsb first is used. remarks 1. the numbers enclosed in parentheses are the pin numbers for the m pd6466gt- . 2. with the m pd6466gt- , the effect of noise through the lead frame can be reduced by connecting the n.c. pins (pin numbers 3, 12, 13, and 22) to gnd. clk cs data pcl v dd cmdct osc out osc in test gnd 10 f 33 h connect to microcontroller input hsync and vsync using negative synchronization output msb first lsb first 30 pf 5 to 30 pf lc module pin number <1> lc module pin number <3> 0.01 f 10 f v dd v dd 100 k w note 1 note 2 note 5 + + 1 (1) 2 (2) 3 (4) 4 (5) 5 (6) 6 (7) 7(8) note 3 8(9) note 3 9 (10) 10 (11) 20 (24) 19 (23) 18 (21) 17 (20) 16 (19) 15 (18) 14 (17) 13 (16) 12 (15) 11 (14) hsync vsync v b v g v r v c1 blk1 v blk v c2 blk2 (r blk ) note 4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pd6466gs/gt (b blk ) note 4 (g blk ) note 4 m m m m m 68 chapter 3 application examples 3.3 external clock forced input to lc oscillation circuit section the external clock input conditions shown in this section are given as a reference example only and are not recommended by nec. this is a reference example for using the m pd6461 or m pd6462 with lc oscillation specified by the mask option or for using the m pd6464a or m pd6465. for external clock input conditions when external clock input is selected for the m pd6461 or m pd6462 mask option or when using the m pd6466, refer to the data sheet of each product. since an lc oscillation circuit is used to generate dot clocks in an osd lsi (with an rgb-system osd lsi, external clock input can be selected), to forcibly input an external clock, you must make the timing similar to when lc oscillation is used (oscillation stopped during hsync period). figure 3-8 shows the timing chart when an external clock is forcibly input. figure 3-8. timing chart for external clock forced input cautions the following restrictions apply when an external clock is used. 1. an interval of period a plus several clocks (4 clocks for the minimum character size) from the hsync falling edge is required to stop the dot clocks. typical period a values for each product are as follows. m pd6461, m pd6462, m pd6464a : 200 ns (typ.) m pd6465 : 500 ns (typ.) the number of clocks, excluding period a, from the hsync falling edge until the dot clocks are stopped depends on the character size in the horizontal direction. for the minimum character size, this value is 4 clocks. for the double character size, this value is 8 clocks. 2. when the hsync rising edge occurs, stabilize hsync with the dot clocks stopped. start the dot clock oscillation after period a elapses from the hsync rising edge. 3. make sure the phase relationship between the external clock and hsync is always fixed. 4. connect the osc in and osc out as follows. osc in : input external clock osc out : open hsync dot clocks a a 4 clocks 69 chapter 4 faq 4.1 all osd lsis q1-1. can external clock input be used? a1-1. when using the m pd6461 or m pd6462 with lc oscillation specified by the mask option or when using the m pd6464a or m pd6465, nec does not recommend the input of external clocks. if continuous external clocks are input, there is a risk that the external buffer that supplies the external clock during the hsync period and the transistor for forcibly stopping oscillation, which is inside the device, in (a) of figure 2-2 dot clock oscillation equivalent circuit may short, an abnormal current may flow in this circuit, and the transistor may be damaged. dot clock lc oscillation or external clock input can be selected by using the mask option for the m pd6461 or m pd6462 or the initialization command for the m pc6466. for details, see 3.3 external clock forced input to lc oscillation circuit section . q1-2. must the serial data and hsync or vsync be synchronized? a1-2. the serial data and hsync or vsync are not synchronized. however, when transferring video ram write data, the command continuous input enable time must be strictly observed. after serial data is transferred, if that data is related to video ram writing, the data is written to video ram by using the dot clock. also, since the dot clock stops and data cannot be written to video ram during the hsync period when character display is on, the data is written to video ram after the dot clock oscillation begins again after the hsync period ends. the time required for writing video ram data is as follows for the m pd6461 or m pd6462. when display is off : 12 character size fosc when display is on : 21 character size + t hwl fosc for details related to the command continuous input enable time, refer to section about command continuous input enable time ( m pd6461, m pd6462, or m pd6465) or busy period for command input ( m pd6464a or m pd6465) in the data sheet of each version. q.1-3. regarding a power-on reset, (1) when the pcl pin is connected to v dd before the power is turned on with high level (power-on clear rating (t pcll ) is not satisfied), and the pcl pin is switched from high level to low level after the power has been turned on, what happens to output from the time the power is turned on until the power- on clear operation is executed? (2) does the osd lsi have any kind of internal switch so that no invalid data is output when the power is turned on in the situation described in (1)? 70 chapter 4 faq a.1-3. (1) the output cannot be predicted. consider the following examples. example 1. if the mode register is pal internal mode when ntsc is used, the black and white diagonal striped pattern may appear since the power-on clear operation is not executed. example 2. since the power-on clear operation is not executed when external video signal mode is established in a video-system osd lsi, when character display is set to on, abnormal screen data may appear according to the video ram contents (which had not been cleared). it may also occur to the output for the background. however, since the external video signal mode display is set to off when the pcl pin is at the low level, the character display output is stopped. (2) the osd lsi contains no kind of internal switch. all nec osd lsis are designed so that the power-on clear operation is executed simultaneously when the power is turned on. since no abnormal data is output if the power-on clear operation is executed, we decided that no switch was required. q1-4. how do you decide the lc oscillation constants? a1-4. nec recommends l = 33 m h, c in = 5 to 30 pf (trimmer capacitor), and c out = 30 pf. for details, see 2.1.1 dot clock oscillation circuit . q1-5. what is the difference between initialization by the video ram batch clear command and that by the power- on clear operation? a1-5. the video ram batch clear command is a software reset, and the power-on clear operation is a hardware reset. for details, see 2.6 osd lsi power-on initialization . q1-6. are fields distinguished? a1-6. an osd lsi does not distinguish fields. q1-7. is data that has been set in video ram maintained as long as the setting is not changed? a1-7. since an osd lsi has an on-chip refresh timer, video ram data is maintained as long as character data is not written to video ram, the power-on clear operation or video ram batch clear command is not executed, or the power is not turned off. q1-8. what is a 2-byte contiguous command? a1-8. a 2-byte contiguous command is a command for writing characters to video ram. for details, refer to the transferring commands section of the data sheet of each version. q1-9. are there any limitations concerning the hsync and dot clock timing relationship? a1-9. as long as the command continuous input enable time is satisfied, there are no specific limitations. for information about the command continuous input enable time, refer to the data sheet of each version. 71 chapter 4 faq q1-10 when transferring a 2-byte contiguous command, why does the command continuous input enable time when display is on include the horizontal synchronization signal (hsync) width? a1-10. in an osd lsi, when display is on, hsync triggers resets for the internal system timing and controls the display position. since the dot clock oscillation is stopped during the hsync period due to these operations, no data is written to video ram. as a result, the command continuous input enable time when display is on includes hsync synchronization signal width. q1-11. when a pal signal is input with equivalent settings for the horizontal/vertical display start positions and dot clock frequency as those used for ntsc signal input, the vertical size of the characters is compressed and space appears at the lower portion of the display screen. what causes this? also, can the same display be output in both the ntsc and pal signal modes? a1-11. this occurs because the number of scan lines differs in the ntsc and pal modes, as shown in figure 4-1. as a result, when a pal signal is input, the horizontal/vertical display start positions and dot clock frequency must be adjusted, and the display area must be moved (the horizontal/vertical display start positions and dot clock frequency are adjusted in the signal mode units). also, since a character non- display area is generated consisting of 53 scan lines per frame (equivalent to approximately 1.5 lines with the smallest size character) when an ntsc signal is input and 143 scan lines per frame (equivalent to approximately 4 lines with the smallest size character) when a pal signal is input (see figure 4-2 ), the same display cannot be output in both signal modes. 72 chapter 4 faq figure 4-1. character display area image 1 C when ntsc and pal signals are input (for equivalent display start position and dot clock frequency) figure 4-2. character display area image 2 C when ntsc and pal signals are input (for center display) character display area maximum: 12 lines 24 columns number of scan lines in character display area maximum: 432 (= 18 dots 12 lines 2 fields) when ntsc signal is input (number of effective scan lines: 485) set the display start position and dot clock frequency so that the character is displayed in the center of the screen. 24 432 485 29 when pal signal is input (number of effective scan lines: 575) set the display start position and dot clock frequency equivalent to those used for ntsc signal input. space appears at the bottom and right side, and the characters are compressed in the vertical direction. 24 432 575 119 character display area maximum: 12 lines 24 columns number of scan lines in character display area maximum: 432 (= 18 dots 12 lines 2 fields) character display area maximum: 12 lines 24 columns number of scan lines in character display area maximum: 432 (= 18 dots 12 lines 2 fields) when ntsc signal is input (number of effective scan lines: 485) set the vertical display start position to 12h, and set the horizontal display start position and dot clock frequency so that the character display area is in the center of the screen. set the vertical display start position to 36h, and set the horizontal display start position and dot clock frequency so that the character display area is in the center of the screen. 24 432 485 29 when pal signal is input (number of effective scan lines: 575) 72 432 575 71 character display area maximum: 12 lines 24 columns number of scan lines in character display area maximum: 432 (= 18 dots 12 lines 2 fields) 73 chapter 4 faq 4.2 video-system osd lsis ( m pd6464a and m pd6465) q2-1. is a crystal oscillator required? a2-1. it is required when 4fsc crystal oscillation is selected according to the oscillation mode control command. this is because the 4fsc signal generated by the oscillator and vco is used as the reference clock for synchronization signal generation when internal video signal mode is set, and the fsc signal generated by dividing this 4fsc signal into four parts is used as the reference clock for internal video signal generation and for the synchronization separation circuit (when external video signal mode is set). use the crystal oscillation control command to set crystal oscillation to on when displaying characters. q2-2. is fsc input required? a2-2. it is required when quadruple oscillation is selected according to the oscillation mode control command. this is because the 4fsc signal generated according to the fsc input is used as the reference clock for synchronization signal generation when internal video signal mode is set, and the fsc signal generated by dividing this 4fsc signal into four parts is used as the reference clock for internal video signal generation and for the synchronization separation circuit (when external video signal mode is set). use the crystal oscillation control command to set crystal oscillation to on when displaying characters. with the m pd6464a or m pd6465, the on-chip quadruple oscillation circuit enables the mounting area and cost to be reduced by using the lc oscillator instead of an expensive crystal oscillator. also, in the lc oscillator only, since the oscillation precision is decreased due to the scattering of each element, a phase locked loop (pll) is formed by inputting fsc, and the 4fsc signal is synchronized with the external fsc signal. q2-3. when fsc input is not used, are there limitations concerning the fsci pin (pin 9) processing? a2-3. connect it to gnd or v dd and do not leave it open. also, use the oscillation control command to select 4fsc crystal oscillation. q2-4. when secam is not used, are there limitations concerning the secam pin (pin 22) processing? a2-4. if the video signal mode control command is used to select an option other than secam, the secam pin (pin 22) is disconnected from the internal circuits by an internal analog switch. therefore, it makes no difference whether something (such as gnd or v dd ) is connected to this pin or it is left open. however, if something is connected, note the absolute maximum rating of the input pin voltage (v in : C0.3 to v dd + 0.3 v). q2-5. are there limitations concerning pin processing when the v c , v blk , hsyo, vsyo, csyin, and n.c. pins (pins 13 through 18) are not used? a2-5. leave them open. q2-6. when o nly the internal video signal is used with the m pd6464a or m pd6465, must the composite synchronization signal (csync) be input? a2-6. the composite synchronization signal (csync) need not be input when internal video signal mode is used. with the m pd6464a or m pd6465, the synchronization signal is autogenerated by using the 4fsc signal generated according to 4f sc crystal oscillation or quadruple oscillation. 74 chapter 4 faq q2-7. what is the scanning method when internal video signal mode is used? a2-7. when internal video signal mode is used, the scanning method is not interlaced. the number of horizontal scan lines is 263 lines per field for ntsc or pal-m mode and 312 lines per field for pal or pal-n mode. q2-8. what are the voltage levels of the composite synchronization signal (csync) input to the csyin pin (pin 17)? a2-8. the csyin pin (pin 17) has normal logic input. therefore, the input levels are as follows according to cmos input regulations. input high level voltage : 0.7 v dd (min.) input low level voltage : 0.3 v dd (max.) q2-9. when display is set to off in the m pd6464a or m pd6465, is the vbsi ? vbso status data through? a2-9. when display is off in external video signal mode, the status is data through. also, when display is off in internal video signal mode, a single screen color is displayed of the color used as the screen background color. q2-10. if the csyin pin (pin 17) is at high level when external video signal mode is used, what is the output status of the hsyo pin (pin 15: horizontal synchronization signal output) and the vsyo pin (pin 16: vertical synchronization signal output)? also, if a 2-byte contiguous command is transferred at this time, is the data written correctly to video ram if the command continuous input enable time (tb2, tb2') is observed? a2-10. the hsyo pin and vsyo pin both remain at low level. also, when a 2-byte contiguous command is transferred, if the csyin pin is at high level, since the ic is always in sync status, the t hwl of the command continuous input enable time becomes infinitely large, and data cannot be written if display is on (since lc oscillation stops, no clock for writing is supplied). therefore, in this situation, data writing to video ram stops when display is on and operates when display is off. q2-11. what kind of drive capacity does the vbso pin (pin 21: composite video signal output) have? a2-11. since the vbso pin of the m pd6464a or m pd6465 only performs through output via an analog switch of the video signal that has been input to the vbsi pin (pin 24: composite video signal input pin), the vbso pin has no drive capacity. therefore, an emitter/follower circuit (buffer) according to a transistor must be added to the vbso pin as shown in 3.1.1 sample m pd6464a or m pd6465 application circuits so that it can drive subsequent circuits. q2-12. what criteria are used when selecting a varactor diode? a2-12. use a varactor diode for which the capacitance changes in the range of approximately 2 to 10 pf with a voltage range on the order of 1 to 4 v. also, since the capacitance of the capacitor connected to pin 12 in figure 3-1 sample m pd6464a or m pd6465 application circuit (when quadruple oscillation is selected) is the value when 1sv163 is used, be sure to re-evaluate the capacitance of the capacitor when the varactor diode is changed. 75 chapter 4 faq q2-13. how do the m pd6464 and m pd6464a differ? a2-13. the m pd6464a has pal-n mode in addition to the video signal modes (ntsc, pal, pal-m, and secam) corresponding to the m pd6464. q2-14. is a pull-up resistor required for the pcl pin (pin 7)? a2-14. it is not required. the m pd6464a or m pd6465 has an on-chip resistor of approximately 50 k w between the pcl pin and v dd . q2-15. if display is set to on after a power-on clear operation is executed and no characters are displayed on the screen even when various types of commands are transferred, what adjustments should be made? a2-15. check the following points and make the corresponding adjustments. ? is the dot clock oscillating? an osd lsi uses the dot clock when writing data to video ram. if the dot clock oscillation is stopped, since the data that is supposed to have been transferred is not written to video ram, the characters are not displayed normally. ? is a composite synchronization signal (csync) being input? in external video signal mode, the m pd6464a or m pd6465 timing generator resets the horizontal control section, vertical control section, and output controller by using the horizontal synchronization signal (hsync) and vertical synchronization signal (vsync) obtained by synchronization separation of csync. it also generates reference signals for counting. if no csync is being input, since the timing generator is not generating these reference signals, the characters are not displayed normally. in internal video signal mode, since hsync and vsync are autogenerated within the device, the characters are displayed even if no csync is being input. ? is 4fsc oscillation occurring? in the m pd6464a or m pd6465, the 4fsc or fsc signal generated by 4fsc crystal oscillation or quadruple oscillation is used for synchronization separation of csync (when external video signal mode is selected) or for generation of the internal video signal and internal synchronization signal (when internal video signal mode is selected). if no 4fsc oscillation is occurring, since signal separation or generation is not being performed, the characters are not displayed normally. 76 chapter 4 faq 4.3 rgb-system osd lsis ( m pd6461, m pd6462, and m pd6466) q3-1. can the dot clock be checked in the m pd6466? a3-1. although the dot clock frequency can be measured by using the clk out pin in the m pd6461 or m pd6462, the m pd6466 does not have this kind of pin. with the m pd6466, the dot clock can be output from the blk1 pin by connecting the test pin to v dd and transferring the test mode command shown below. 2-byte command (msb) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1011000000001100 2-byte command (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 0000110100110000 caution use this command only for checking the dot clock. q3-2. when external clock input timing is used, what happens if t h-c is less than 30 ns (min.) (for example, when the hsync rising edge and the external clock falling edge overlap (t h-c @ 0 ns))? a3-2. an osd lsi uses hsync for the horizontal control counter reset signal and uses the external clock for the horizontal control counter clock. if the t h-c 3 30 ns rating cannot be satisfied, the hsync rising edge and the external clock falling edge may overlap within the horizontal control counter depending on the arrival delay time difference of hsync and the clock to the horizontal control counter (due to manufacturing variations and conditions of the usage environment such as power source voltage or temperature). if the edges overlap, the timing of the cancellation of a counter reset due to hsync and the count increment will overlap. therefore, an unstable condition occurs in which the edge overlapped by the clock may or may not be counted as the first edge. actually, since both hsync and the clock have a slight amount of jitter, the condition in which that edge is or is not counted is repeated. as a result, the horizontal display position shifts by one clock (one-dot horizontal jitter occurs). q3-3. what does the synchronization protection circuit do? a3-3. the synchronization protection circuit prevents vertical jitter of the display character by generating a pseudo hsync signal. for details, see 2.3.1 synchronization protection circuit . q3-4. in the m pd6461 or m pd6462, when the dot clocks external clock input is selected by using the mask option, can lc oscillation occur? a3-4. when the dot clocks external clock input is selected by using the mask option, no dot clock lc oscillation can occur. when external clock input is selected, since the oscillation stage of the lc oscillation circuit is completely disconnected from the pin (see (b) in figure 2-2 dot clock oscillation equivalent circuit ), even if an external lc oscillator is attached, it cannot be made to oscillate. 77 chapter 4 faq q3-5. are there any limitations concerning the clocks that are input when an external clock is selected? a3-5. as criteria for the external clock, input the following amplitude and duty rate. input amplitude : input high level voltage = 0.7 v dd (min.) input low level voltage = 0.3 v dd (max.) duty rate : set at 50% (typ.) also, make the dispersion range within 40 to 60%. for information about the external clock fall ? synchronization signal rise time (t c-h ), synchronization signal rise ? external clock fall time (t h-c ), and rise slew rate (ts), refer to the electrical specifications in the data sheet. q3-6. what is the approximate output impedance of each output pin? a3-6. the m pd6461, m pd6462, and m pd6466 have a cmos configuration, and the output impedance is approximately 100 w or less. q3-7. is it possible to change the background color of a specific area? a3-7. it is possible. since the background color is set in terms of screens, first set the character inversion on/ off specification command (which is set in terms of screens; for the m pd6466, character color inversion on/off specification command), to on. then, set the character inversion specification bit (for the m pd6466, character color inversion specification bit) of the display character control command, which is set in terms of characters, to on (see figure 4-3 ). figure 4-3. sample display using character inversion remark the background color of the characters for which inversion is on will be the character color (which can be set in terms of characters). the character color when inversion is on is black (for or the m pd6466, white also can be specified). navigation tv video cd md character inversion on 78 chapter 4 faq q3-8. if the character display is corrupted or if no character is displayed, what adjustments should be made? a3-8. check the following points and make the corresponding adjustments. ? is the dot clock oscillating? an osd lsi uses the dot clock when writing data to video ram. if the dot clock oscillation is stopped, since the data that is supposed to have been transferred is not written to video ram, the characters are not displayed. ? are the hsync and vsync input? the timing generator resets the horizontal control section, vertical control section, and output controller by using the hsync and vsync that were input, and generates reference signals for counting. if hsync and vsync are not being input, since the timing generator is not generating reference signals, the characters are not displayed. ? is the command executed within the command continuous input enable time? if the command continuous input enable time is not observed, the data that is supposed to have been transferred is not written to video ram, and the character display is corrupted. 79 chapter 5 development tools 5.1 overview of development tools nec provides the osd lsi development tools introduced below. these all are available for short-term rental. when necessary, contact an nec distributor or nec sales representative. ? character pattern editor for windows ? character rom verification and evaluation board ? osd lsi evaluation board overviews of each tool are presented below. (1) character pattern editor for windows this is a tool for creating the character data to be installed in the character generator rom. its main features are described below. for details, refer to the osd lsi character pattern editor users manual . ? supports windows 3.1 and windows 95 ? supports fd order reception floppy disks are used for the mask rom code ordering media. use *.out for data save files. the following table shows the floppy disk physical format when ordering mask rom code from nec. size number of number of tracks number of sectors record length recording recording surfaces capacity 3.5 inch double sided 77 tracks/side 8 sectors/track 1024 bytes/sector 1261568 bytes remarks ms-dos : floppy disk formatting capacity: select 1 mb (format d: /m) pc dos : floppy disk formatting capacity: select 1.2 mb (format12) note windows 3.1 : floppy disk formatting (f) capacity (c): select 1 mb windows nt tm : floppy disk formatting (f) capacity (c): select 1.25 mb windows 95 : floppy disk formatting (f) capacity (c): select 1.2 mb note the floppy disk drive must support 1.2-mb diskettes. register $fdd12.sys in config.sys. for details, refer to a pc dos manual. for details related to mask rom code ordering, refer to the information document, rom code ordering method . ? maintains upward compatibility with dos-version environment data save files (*.out and *.sav) created by the conventional dos-version editor can be used, and compatibility with the dos-version editor is maintained. ? provides simple operations and an excellent user interface by using the toolbar, you can execute frequently used functions by clicking a single button. also, by using multi-document interface (mdi) mode, you can manipulate multiple files (data) on the same screen. 80 chapter 5 development tools (2) character rom verification and evaluation board this is a tool for verifying the character that was created by the character pattern editor (using *.out for data files) on an actual monitor screen before ordering the mask rom. use this board with the connections shown in figures 5-1 and 5-2. remark ms-dos 3.3 is required to run the character rom verification and evaluation board system software. in addition, the character rom verification and evaluation board must be connected to a personal computer by using the supplied interface (i/f) board. when evaluating character data, a pc-98 or pc-98-compatible computer (equipped with an expansion slot) must be used as the personal computer where this software can be activated and this i/f board can be connected. figure 5-1. rom verification board connection diagram for rgb display pc98 insert in expansion slot system software (os: ms-dos 3.3) i/f board logic section cn9 cn6 cn2 cn1&3 ram section 33 cn8 video out cn7 cn5 cn4 digital v dd & gnd ? ? ? connect to power supply v cc = v dd = 5.5 v 1 a n 2 b e 3 c c 4 d 5 e 6 f 7 g 8 h 9 i rgb 21-pin multi-connector and cable tv monitor video in video signal input analog v cc & gnd 81 chapter 5 development tools figure 5-2. rom verification board connection diagram for vcr display (4) osd lsi evaluation board this is a tool for evaluating the functions of nec standard products or of engineering samples (es), etc. after the mask rom has been ordered. there are two types of osd lsi evaluation boards. the m pd6464a and m pd6465 evaluation board is for video- system osd lsis and the m pd6461, m pd6462, and m pd6466 evaluation board is for rgb-system osd lsis. use these boards with the connections shown in figures 5-3 and 5-4. remark ms-dos 3.3 is required to run the osd lsi evaluation board system software. when evaluating osd lsis, a pc-98 or pc-98-compatible computer must be used as the personal computer where this software can be activated. pc98 insert in expansion slot system software (os: ms-dos 3.3) i/f board logic section cn9 cn6 cn2 cn1&3 ram section 33 cn8 video out cn7 video in cn5 cn4 analog v cc & gnd digital v dd & gnd ? ? ? connect to power supply v cc = v dd = 5.5 v video signal input rgb 21-pin multi-connector and cable tv monitor 1 a n 2 b e 3 c c 4 d 5 e 6 f 7 g 8 h 9 i 82 chapter 5 development tools figure 5-3. video-system osd lsi evaluation board connection diagram figure 5-4. rgb-system osd lsi evaluation board connection diagram pc98 printer cable pd6464a and pd6465 evaluation board + 5-v power supply vbsi vbso video signal input vcr, ld, sg, etc. system software (os: ms-dos 3.3) tv monitor 1 a 2 b 3 c 4 d 5 e 6 f 7 g 8 h 9 i m m just imagine nec multimedia pc98 printer cable pd6461, pd6462, and pd6466 evaluation board + 5-v power supply rgb 21-pin multi-cable system software (os: ms-dos 3.3) pd6461, pd6462, and pd6466 conversion board tv monitor 1 a 2 b 3 c 4 d 5 e 6 f 7 g 8 h 9 i video signal input vcr, ld, sg, etc. mm m m m m just imagine nec multimedia 83 chapter 5 development tools 5.2 concerning osd lsi mask rom ordering the tools described in 5.1 overview of development tools can be used for ordering mask rom code according to the procedure shown in figure 5-5. for details related to mask rom code ordering, refer to the information document, rom code ordering method . figure 5-5. osd lsi mask rom code ordering procedure (for fd order reception) note these tools are rented. for details, contact an nec distributor or nec sales representative. select product to be used order mask create characters using the character pattern editor note supporting windows 3.1 or windows 95 and fd order reception use the character rom evaluation board note to evaluate the created characters on the screen record the final character data (*.out file) on the rom ordering media (fd) and send it to nec verify whether the contents of the return media match the final character data nec receives the media, creates the return media, and returns it 84 [memo] although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-2719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6462-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: 044-435-9608 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 00.6 name company from: tel. fax facsimile message |
Price & Availability of UPD6462GS-XXX
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |